FIG. 18 is a block diagram of a configuration example of an information processing system. A system 100 illustrated in FIG. 18 is provided with a control unit 110, a CPU (Central Processing Unit) 120, a memory 130, and an I/O (Input/Output) channel 140.
The control unit 110 is adapted to arbitrate memory accesses from the CPU 120 or the I/O channel 140 to the memory 130, and, for example, a system controller is exemplified.
In case where a load verification is carried out with respect to the system 100 illustrated in FIG. 18, in a load generation apparatus or software, a method of frequently generating the memory accesses from the CPU 120 or the I/O channel 140 to the memory 130 is employed.
It may be noted that a method is proposed in which the load generation apparatus creates a pattern for DMA (Direct Memory Access) for changing a load target address to a memory space at an arbitrary address interval and executes the DMA to apply loads of various access patterns to an examination target system.
Also, in a server computer network, a configuration is also proposed in which a performance test system is provided with a test logic segment and a switched network, and load generated from a test target apparatus is concentrated on a particular test target apparatus.
Japanese Laid-open Patent Publication No. 2008-059338 and Japanese Laid-open Patent Publication No. 2008-191837 are examples of related art.
In recent years, a system provided with a plurality of CPUs and a plurality of control units is developed.
In the above-mentioned system, a method is proposed of carrying out a load dispersion between the control units so that the accesses based on access requests to the memory by the plurality of CPUs are not concentrated on one control unit.
For the load dispersion, for example, a configuration is proposed in which with respect to the memory accesses to a continuous area of a high use frequency, in order that the memory accesses are not concentrated on the individual control units, a control unit that arbitrates the memory accesses for each of the memory addresses is allocated.
Also, when the accesses are generated from the plurality of CPUs to the same address of the memory, the above-mentioned system control unit is adapted to alleviate the loads applied on the control unit and the memory by directing the subsequent access destination of the CPU to a cache memory of the CPU that has accessed the relevant memory address beforehand.
At this time, in a case where the control unit does not direct the subsequent access destination of the CPU to a cache memory of another CPU, the control unit carries out an order assurance of the plurality of CPUs in an order of the accesses to the same address of the memory and stops the accesses of the subsequent CPUs.
Also, in a case where the accesses are generated from the plurality of CPUs to the same address of the memory, a situation occurs that the address requests to the same address are held up, and accordingly the memory existing in the lowermost stream of the accesses becomes a bottle neck of the system.
On the other hand, in a case where the load verification with respect to the above-mentioned system is carried out, even when the accesses are generated from the plurality of CPUs to the same address of the memory, the load with respect to the control unit is decreased because of the reference to the cache memory by the respective CPUs, the order assurance by the control unit, the hold-up of the access requests in the memory, and the like.
Therefore, in a case where the load verification with respect to the above-mentioned system is carried out, with the load generation apparatus or software, it is difficult to frequently randomly generate the memory accesses from the plurality of CPUs to the memory and concentrate the accesses on the individual control units.
That is, as described above, by the load dispersion by the system, as one of the control units among the plurality of control units is allocated to each of the memory addresses, the access destination (memory address) of the memory access is random. Thus, it is desirable to concentrate the loads on a particular control unit. Also, because the access destination (memory address) of the memory access is random, a memory access where the access is directed to the cache memory of the CPU may also be generated.
Then, in the above-mentioned case, the load with respect to the control unit is decreased, and the load verification with respect to the system is deteriorated.
Also, according to the above-mentioned method in which the load generation apparatus creates the pattern for the DMA and executes the DMA, the system provided with the plurality of control units that perform the above-mentioned load dispersion is not supposed as the target. Therefore, according to the above-mentioned method, it is desirable to create a state transition in which the loads caused by the memory accesses from the CPU spread over the plurality of control units. Also, according to the above-mentioned method, the situation in which the accesses are generated from the plurality of CPUs to the same address of the memory and the decrease in the load on the control unit is not taken into account.
In the system including the plurality of control units where the load dispersion is carried out, a method of concentrating the load on the particular control unit is not yet proposed.
In the above, the case has been described in which the memory accesses from the plurality of CPUs are arbitrated by the plurality of control units, but a similar problem occurs also in a case where the memory accesses are arbitrated by the plurality of control units when the accesses are made to the storage unit such as the memory via interfaces such as a plurality of I/O channels. In addition to that, a similar problem occurs also in another system having a function of switching the plurality of control units on the basis of the address of the access destination.